16-bit SRAM – Multibody, Multi-Domain Physical Model in MapleSim – Maplesoft

16-bit SRAM

In this model, a 1-bit 6T SRAM subsystem is connected in words of 4 bits to create a 16-bit SRAM. The 1-bit subsystems are made using NMOS and PMOS transistor components with a positive threshold voltage of 0.7 V and a negative threshold of -0.7 V. The bit line inputs are controlled by the WriteLowReadLow and WriteHighReadHigh subsystems which toggle writing vs reading for their corresponding values.

The write line for word 1 is set high for half of the first cycle to allow the bits in the first row to be written then set low for the second half of the cycle to allow reading of stored values. The write line for word 2 is set high to allow writing during the first half of the second cycle and set low again the last half of the second cycle to allow reading of the newly written values. The write lines for words 3 and 4 are held low.

The values stored inside the bits of SRAM cells is output in the probes labeled 'Q' and the values being written are viewable in the probes labeled 'B'.

This model was created with MapleSim 2020.1
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Model Images
  • img_model The model schematic of the system
  • img_results Plots of the simulation results
  • img_subsystem Schematic of one cell of the SRAM