DLATREGSRL
Level-sensitive register bank with active-low reset and set
Description
Connections
Parameters
Modelica Standard Library
The DLATREGSRL component is a level-sensitive digital register with a high enable and active-low reset and set inputs and a configurable output delay.
The strength parameter specifies a map on logic signals. Its value consists of a symbol, Sxlh, with xlh being one of the following: X01,X0H,XL1,X0Z,XZ1,WLH,WLZ,WZH,W0H,WL1. The three subscripts define the map:
A U always maps to a U.
{X,Y,W,-} map to the first subscript (x).
{0,L} map to the second subscript (l).
{1,H} map to the third subscript (h).
For example, SX0H means {X,Y,W,-} map to X, {0,L} map to 0, {1,H} map to H.
The ResetSetMap parameter is a two-dimensional, 9 by 9 array that maps the reset and set inputs to the integers 1 to 8, inclusive. The following table defines the output signal levels associated with each integer. Each symbol in a cell corresponds to an output level; the actual output level is determined by the strength parameter map.
1
2
3
4
5
6
7
8
U
0
UX
-1UX
X
-0UX
-dUX
d = dataIn
DataIn
Enable
Reset
Set
DataOut
*
X or U
X or U or 1 or NC
X or U or 0 or NC
X or U or NC
NC
Name
Modelica ID
set
Active-low set
reset
Active-low reset
enable
Active-high enable
dataIn
Data input
dataOut
Data output
Default
Units
tHL
s
High->Low delay
tLH
Low->High delay
strength
SX01
Output strength
n
Data width
The component described in this topic is from the Modelica Standard Library. To view the original documentation, which includes author and copyright information, click here.
See Also
Digital Components
Digital Registers
Electrical Library
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