DFFSR
Edge-triggered register bank with configurable reset and set
Description
Connections
Parameters
Modelica Standard Library
The DFFSR component is an edge-triggered digital flip-flop register with configurable reset and set inputs. A positive transition (1-Trns) of the clock causes the input data to be latched and appear at the output.
Truth Table for active-low reset and set
DataIn
Clock
Reset
Set
DataOut
Map
*
U
1
0
2
3
X
6
X or U
4
X or U or 1 or NC
5
X or U or 0 or NC
7
X-Trns
X or U or NC
8
1-Trns
0-Trns
NC
Symbol Definitions
Symbol
Definition
do not care
L.‵U‵
L.‵0‵ or L.‵L‵
L.‵1‵ or L.‵H‵
L.‵X‵ or L.‵W‵ or L.‵Z‵ or L.‵-‵
no change
Clock Transition Definitions
0→1
~→0 or 1→* or X|U→X|U
0→X or X|U→1
Name
Modelica ID
set
Set input
reset
Reset input
clock
Positive edge-triggered clock input
dataIn
Data input
dataOut
Data output
Default
Units
ResetSetMap
[1]
function selection by [reset, set] reading
strength
SX01
Output strength
n
Data width
[1] ResetMap=111111111147244724158255825163266326147244724147244724158255825163266326147244724
The component described in this topic is from the Modelica Standard Library. To view the original documentation, which includes author and copyright information, click here.
See Also
Digital Components
Digital Registers
Electrical Library
Download Help Document